The present invention relates to integrated circuit chips, and more specifically, to field effect transistors (FET) with improved capacitance.
The speed of an FET is largely determined by the distance across the gate. Transistors with a shorter gate conductor distance have a shorter spacing between source and drain and are generally faster. The industry has moved to photolithography equipment that provides a shorter wavelength of light and a higher numerical aperture lens with each generation of integrated circuits to permit decreasing this dimension of the gate. However, these changes have frequently increased cross chip line width variation. Furthermore, these changes have resulted in higher gate resistance.
Further, as semiconductor device dimensions shrink, the adverse impact of parasitics such as gate-to-contact parasitic capacitance and fringing capacitance on device performance becomes more and more severe, particularly for semiconductor devices with raised source/drain (RSD). Reducing parasitic capacitance is critical for improving circuit performance while maintaining low power.